The present disclosure relates generally to the field of semiconductor device reliability testing, and more particularly to characterizing the impact of bias temperature instability on threshold voltage degradation of semiconductor devices that operate in the radio frequency range. Complementary metal-oxide-semiconductor (hereinafter “CMOS”) technology is utilized for constructing integrated circuits wherein complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors are typically utilized for logic functions.
The application of CMOS technology in radio-frequency (hereinafter “RF”) integrated circuits has developed due to their low cost and broad applications, for example, switches and power amplifiers. Such devices can experience large RF swing voltages, which can exceed their maximum allowed DC bias voltage and result in device life-time reduction. Bias temperature instability (hereinafter “BTI”) is a CMOS device reliability failure mechanism, which typically results from high gate to source/drain bias at elevated temperature. BTI effects includes negative bias temperature instability (hereinafter “NBTI”) and positive bias temperature instability (hereinafter “PBTI).
NBTI effects are seen when a negative gate voltage stress is applied to a p-channel CMOS transistor, and the effects diminish rapidly during the recovery time immediately following the removal of the stress. Similarly, PBTI effects are seen in N-channel CMOS devices, particularly in those with high-k gate dielectrics. The reliability of RF CMOS integrated circuits may be addressed by stressing the device under RF power and characterizing, for example, hot carrier transport behavior, gate dielectric damage, and device failure mechanisms. However, traditional RF characterization methods for RF stress testing involve complicated tuning and calibrations and are difficult to develop. The typical set up for RF characterization utilizes a six (6) pad RF structure and two Ground-Signal-Ground probes, wherein a signal pad is in communication with the gate and drain terminals of the transistor, and wherein the source and drain terminals therein are grounded. However, the typical configuration setup required for RF characterization will not support RF stressing, which requires that the source and body terminals are in communication with a signal pad.